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Single Precision Load

Actual hardware has a delay between a load instruction and the time when the data reaches the register. The electronics of main memory handles all bit patterns in the same way, so there is the same delay no matter what the bit patterns represent.

In SPIM there is an option that disables the load delay. For this chapter, disable the load delay. (Floating point is tricky enough already).

Loading a single precision value is done with a pseudoinstruction:

l.s   fd,addr     # load register fd from addr
                  # (pseudoinstruction)

This instruction loads 32 bits of data from address addr into floating point register $fd (where $fd is $f0, $f1, ... $f31. Whatever 32 bits are located at addr are copied into fd. If the data makes no sense as a floating point value, that is OK for this instruction. Later on the mistake will be caught when floating point operations are attempted.


Every one of the 232 patterns that 32 bits can form is a legal two's complement integer.

Are some 32-bit patterns not legal as floating point values? Hint: think about how zero is represented.